A VDMOS device incorporates a semiconductor wafer in which source, body and drain regions of alternate conductivity type are disposed in series. The body region is disposed adjacent to a wafer surface, and the source and drain regions are located so as to define the length and width of a channel region in the body region at that surface. An insulated gate electrode is disposed on the wafer surface over the channel region.
During device operation, an appropriate voltage on the gate electrode inverts the conductivity type of the body region in that portion of the channel region that is contiguous with the wafer surface; so as to form an inversion channel contiguous with the wafer surface. The remainder of the channel region comprises a depletion region which is associated with this inversion channel. For a particular device structure, the depth of the depletion region portion of the channel region is determined by the magnitude of the voltage applied to the gate electrode, and the inversion channel permits current flow between the source and drain regions. Thus, device operation is described as being unipolar in nature, with electron or hole flow being selectively modulated by an applied voltage to the gate. A conventional VDMOS structure is further described in U.S. Pat. No. 4,145,700, POWER FIELD EFFECT TRANSISTORS, C. J. Jambotkar, Mar. 20, 1979.
Inherent in the source/body/drain structure of a VDMOS device is a parasitic NPN or PNP bipolar transistor. In that the presence of this parasitic transistor is detrimental to FET performance, various efforts have been employed so as to reduce its gain. An example of such an effort is described in U.S. Pat. No. 4,072,975, INSULATED GATE FIELD EFFECT TRANSISTOR, A. Ishitani, Feb. 7, 1978. In an effort to even more effectively reduce the effects of the parasitic bipolar transistor the configuration of the present invention was conceived. Additionally, the structure of the present invention may provide greater punchthrough protection and lower on-resistance. Furthermore, the invention can yield a device having a threshold voltage which is lower than that of an equivalent device not incorporating the invention.